# Designing a RISC-V CPU, Part 1: Learning hardware design as a software engineer **URL:** \ **Category:** In The News\ **Tags:** learning, design, hardware, risc, cpu, in-the-news\ **Created:** [19 February 2021 14:27 UTC](https://forum.devtalk.com/t/designing-a-risc-v-cpu-part-1-learning-hardware-design-as-a-software-engineer/7187 "2021-02-19T14:27:17Z")\ **Posts on this page:** 1\ **Page:** 1
**Author:** ![CommunityNews](https://forum.devtalk.com/user_avatar/forum.devtalk.com/communitynews/32/1113_2.png) [@CommunityNews](https://forum.devtalk.com/u/CommunityNews)\ **Post date:** [19 February 2021 14:27 UTC](https://forum.devtalk.com/t/designing-a-risc-v-cpu-part-1-learning-hardware-design-as-a-software-engineer/7187/1 "2021-02-19T14:27:17Z")
> # Designing a RISC-V CPU, Part 1: Learning hardware design as a software engineer > > Tue 16 February 2021 > > I have no experience in digital logic design. That is, I didn’t until I recently decided that I would like to try designing my own CPU and running it on an FPGA! If you too are a software engineer with a vague interest in hardware design, I hope this series of posts about what I’ve learnt will be helpful and interesting. In this first installment, I hope to answer these questions: > > - What is digital logic design? > - How do I get started, and what tools might I use? > > In future installments, I will go into more detail about my CPU design and the RISC-V architecture, as well as hopefully answering these questions: > > - What about digital logic design is fundamentally different from software design? > - What about digital logic design is similar to software design? > > You can see the code for my CPU at the time of writing [here](https://github.com/lochsh/riscy-boi/tree/47e94dc6e9665f73c871add002c34d1516fd5106)or an up to date version [here](https://github.com/lochsh/riscy-boi). [https://mcla.ug/blog/risc-v-cpu-part-1.html](https://mcla.ug/blog/risc-v-cpu-part-1.html) _This thread was posted by one of our members via one of our news source trackers._